1. Field of the Invention
The present invention relates to comparator circuits. More particularly, it relates to a comparator having a latching circuit, in which the coupling of the input signal into the latch and/or the coupling of the output signal from the latch are designed to minimize the internal loading of the latch. The reduced loading allows this comparator circuit, when it is switched from acquisition (or tracking) mode to latching (or regenerative) mode, to resolve a very small input difference into a full logic level more rapidly than any previously known comparator circuit implemented with a given transistor technology.
A latching comparator determines, at a particular instant, which of two voltages is larger, or equivalently, determines the sign of a voltage difference. The output of the comparator is generally a logic voltage level compatible with the inputs of some particular logic circuitry. If the voltage difference to be resolved is small compared to the logic voltage swing, some period of time is required after the comparator is clocked for the voltage to be amplified to a recognizable logic level. A small input voltage difference generally begins to grow at an exponential rate, characterized by a so-called xe2x80x9cregeneration time constantxe2x80x9d, when the comparator clock signal is switched. The smallest voltage difference that can be resolved by the comparator in a given period of time is limited by the value of this constant. This means that if an input difference is too small it will not produce a valid logic signal in the allotted time interval.
2. Description of the Related Art
The best regeneration time for prior art comparator circuits is achieved with a differential current-mode latch with the input and output coupled into taps in the collector load resistors of the latch. See, for instance, R. Van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters, Klever Academic Publishers, 1994, pp. 121-122. However, the input transistor collectors and output transistor bases still significantly load the latch.
In the usual prior art implementation of a clocked latching comparator, a clock signal switches the comparator between an acquisition mode and a latching mode. In the acquisition mode the comparator has a relatively low gain and the output follows the signal input. When the comparator is clocked into the latching mode, positive feedback is enabled so that any arbitrarily small signal that is present will regenerate and drive the latch to its full output swing. When the signal is small, the rate of growth is proportional to the signal voltage present at any given time. This means that the regeneration is characteristically exponential in time, with a regeneration time constant Tr. If the clock timing for the comparator allows some time T for regeneration, the input signal should be at least exp(xe2x88x92T/Tr)xc2x7Vsw to be resolved, where Vsw is the value of a full logic swing. Smaller inputs will not be able to reach a full logic swing and may not be correctly resolved by the subsequent logic. This undesired condition is referred to as comparator (or latch) metastability.
The regeneration time constant for a comparator (or, in general, any latch) is determined primarily by the gain in the positive feedback loop and by the loading of various capacitances in the circuit.
FIG. 1 shows a simplified electrical circuit of a prior art differential current-mode latch. An example of this circuit can be for example found in U.S. Pat. No. 4,083,043 to D. R. Breuer and in D. R. Breuer, xe2x80x98High-speed A/D Converter Monolithic Techniquesxe2x80x99, International Solid State Circuits Conference Proceedings, February 1972, pp. 146-147 and 228.
The circuit of FIG. 1 comprises an input differential pair of transistors Q1-Q2, a latch differential pair of transistors Q3-Q4, a clock differential pair of transistors Q5-Q6, load resistors R1 and R2 and a current source I1. The clock differential pair Q5-Q6 steers the current from the current source I1 into either the input differential pair Q1-Q2 when the clock input signal CLK is high, or into the latch differential pair Q3-Q4 when the clock signal CLKX is high. CLK and CLKX are complementary signals; when one is low the other is high and vice versa.
When the clock signal CLK is high, the input differential pair Q1-Q2 operates as a transconductor which converts the input voltage difference at the bases of Q1 and Q2 to a difference in the collector currents of Q1 and Q2. The collector currents flow into the high impedance of the load resistors R1 and R2 at the nodes A and B of FIG. 1 and create a voltage difference between these nodes which is an amplified replica of the input voltage difference at the bases of Q1 and Q2.
When the differential clock voltage is switched so that CLK goes low and CLKX goes high, the input pair Q1-Q2 is deactivated and the latch pair Q3-Q4 becomes active. The latch pair Q3-Q4 and the load resistors R1 and R2 form a very high gain positive-feedback amplifier such that any voltage present between A and B will be amplified (or xe2x80x9cregeneratedxe2x80x9d) until the latch is driven to a saturated output. The output of the comparator may be taken either directly from A and B as shown in FIG. 1 or through some sort of buffer amplifier that has its inputs connected to A and B.
To use this circuit as a strobed comparator, the voltage difference to be compared is applied between the input signals IN and INX while the clock signal CLK is high. At the time the comparison is to be made, the clock signal CLKX is rapidly switched high so that the amplified input voltage differential serves as the starting point for the latch to regenerate to a saturated output level. The rate of regeneration depends inversely on the capacitive loading at the high impedance nodes A and B. In a conventional integrated circuit implementation of the comparator, this loading essentially consists of:
a) collector-base and base-emitter capacitances of Q3 and Q4;
b) parasitic collector-substrate capacitances of Q3 and Q4;
c) substrate capacitance of the resistors R1 and R2;
d) collector-base capacitance of Q1 and Q2;
e) parasitic collector-substrate capacitances of Q1 and Q2; and
f) the output load, which is usually at least the collector-base and base-emitter capacitances of emitter followers or of a differential pair.
Items a, b, and c above are inherently part of the regenerative latch, whereas items d, e, and f are associated with the circuitry used to couple signals into and out of the latch.
In order to use this circuit as a high speed latching comparator and to reduce the loading due to the above circumstances, various modifications have been made up to now. These modifications have included in particular the use of emitter followers in the latch, and a split collector load resistor. These modifications have provided a higher loop gain in the latch, a higher collector-base voltage for Q3 and Q4, together with some degree of isolation of the capacitances of the input pair, Q1 and Q2, and of the output load from the loop involving Q3 and Q4 when the regeneration takes place. However, also when taking into account all of these modifications, the value of the regeneration time constant has always been limited to some degree by the above loadings.
The present invention solves the aforementioned prior art problems by providing a comparator, having a comparator input receiving a first input signal and a second input signal during an acquisition mode, and having a comparator output outputting a comparator output signal indicative of the largest between the first input signal and the second input signal, the comparator comprising: a cross-coupled regenerative latch for regenerating, during a latching mode, a signal which is indicative of a difference between the first input signal and the second input signal; a circuit connected to the cross-coupled regenerative latch, operating as a voltage follower during the acquisition mode and as a cascode amplifier stage during the latching mode; and a clocking circuit for switching the comparator from the acquisition mode to the latching mode and vice versa.
According to a second object of the present invention, a comparator is provided, having a comparator input receiving a first input signal and a second input signal during an acquisition mode, and having a comparator output outputting a comparator output signal indicative of the largest between the first input signal and the second input signal, the comparator comprising:
a cross-coupled regenerative latch for regenerating, during a latching mode, a signal which is indicative of a difference between the first input signal and the second input signal, said cross-coupled regenerative latch comprising:
a first and a second resistor, each of said first and second resistor having a first end and a second end, and a first and a second bipolar transistor, wherein the collector of the first transistor and the base of the second transistor are connected to the first end of the first resistor, the collector of the second transistor and the base of the first transistor are connected to the first end of the second resistor, and the emitter of the first transistor is connected to the emitter of the second transistor;
a circuit connected to the cross-coupled regenerative latch, operating as a voltage follower to couple the comparator input into the latch during the acquisition mode and as a cascode amplifier stage to couple a latch state to the comparator output during the latching mode, said circuit comprising:
a third and a fourth resistor, each of said third and fourth resistor having a first end and a second end, and
a third and a fourth bipolar transistor, wherein the collector of the third transistor is connected to the second end of the third resistor and the collector of the fourth transistor is connected to the second end of the fourth resistor; and
a clocking circuit for switching the comparator from the acquisition mode to the latching mode and vice versa.
According to a further object of the present invention, a comparator is provided, having a comparator input receiving a first input signal and a second input signal during an acquisition mode, and having a comparator output outputting a comparator output signal indicative of the largest between the first input signal and the second input signal, the comparator comprising:
a cross-coupled regenerative latch for regenerating, during a latching mode, a signal which is indicative of a difference between the first input signal and the second input signal, said cross-coupled regenerative latch comprising:
a first and a second resistor, each of said first and second resistor having a first end and a second end, and
a first and a second field effect transistor, wherein the drain of the first transistor and the gate of the second transistor are connected to the first end of the first resistor, the drain of the second transistor and the gate of the first transistor are connected to the first end of the second resistor, and the source of the first transistor is connected to the source of the second transistor;
a circuit connected to the cross-coupled regenerative latch, operating as a voltage follower to couple the comparator input into the latch during the acquisition mode and as a cascode amplifier stage to couple a latch state to the comparator output during the latching mode, said circuit comprising:
a third and a fourth resistor, each of said third and fourth resistor having a first end and a second end, and
a third and a fourth field effect transistor, wherein the drain of the third transistor is connected to the second end of the third resistor and the drain of the fourth transistor is connected to the second end of the fourth resistor; and
a clocking circuit for switching the comparator from the acquisition mode to the latching mode and vice versa.
According to a preferred embodiment of the present invention, the cross-coupled regenerative latch comprises a first and a second resistor, each of the first and second resistor having a first end and a second end, and a first pair of three-terminal devices connected therebetween and to the first end of the first and second resistors.
Moreover, according to this preferred embodiment, the circuit comprises a second pair of three-terminal devices (for example bipolar transistors or field effect transistors) connected to the second end of the load resistors, the second pair of three-terminal devices operating as voltage followers to couple the first input signal and the second input signal into the second end of the load resistors and operating as cascode amplifier stages to couple the currents in the load resistors to the comparator output.
In particular, the comparator circuit according to the present invention eliminates all extraneous loading from the positive feedback when the regeneration takes place, so that a faster regeneration rate (shorter regeneration time constant) can be achieved. More particularly, all the extraneous loading associated with the input circuitry or the output circuitry is eliminated.
The shorter regeneration time constant of the comparator circuit according to the present invention allows the comparator circuit to resolve a smaller voltage difference in a given time, or resolve a given voltage difference more quickly or to reduce the probability that the comparator output will not be a valid logic signal to properly drive subsequent circuitry. In particular, the regeneration time constant is about the half of the regeneration time constant of the best prior art comparators.
The improved regeneration time constant of the disclosed comparator circuit will be the enabling technology for improved resolution or lowered noise floor in several types of high speed analog to digital converters. Also, particularly for parallel architectures that use large numbers of comparators, the comparator according to the present invention will allow a given speed and resolution to be achieved with lower power dissipation.
The present invention will be best understood from the following description when read in conjunction with the accompanying drawings.